This invention relates to the protection of semiconductor devices, particularly field effect transistors, should they be required to dissipate excessive power such as may be developed when the load being controlled by the device or field effect transistor has become short circuited.
A power field effect transistor is typically a VMOS device having gate, drain and source electrodes. In a usual application, a load is connected between a source of voltage and the drain electrode, the source electrode is connected to return and the gate electrode receives typically 10 volts DC for reducing the drain to source resistance from a high value to a low value thus allowing energization of the load.
If a field effect transistor is required to dissipate too much energy or power when it is turned on, the large current flow and large voltage will cause burning of the semiconductor material which, of course, leads to the destruction of the device. Such excessive power can result, for example, from a shorted load where the voltage from the voltage source is applied directly to the drain terminal. Under such conditions, when the field effect transistor is gated on and the load is short circuited, the voltage at the drain terminal of the field effect transistor reamins high but the transistor also begins conducting current. The large current flowing through the transistor and full voltage being applied to the drain terminal of the transistor produces a large amount of power which the transistor must dissipate. Since current is flowing through the transistor and source voltage is being applied to the drain of the transistor, the transistor is incapable of dissipating so much power and the transistor will be destroyed.
Typical prior art approaches for preventing such destruction of field effect transistors include a fuse in series with the load which will open circuit whenever the current flowing therethrough becomes too large. However, such a protection device is inadequate because it both limits the current capabilities of the circuit and requires replacement when it open circuits. Latching type limit devices are also known which will turn the FET off whenever the FET is required to dissipate excessive power. However, because this type of limit is a latching device, it must be manually reset whenever it is required to function. Finally, power limiting resistors are sometimes connected in series with the drain-source circuit of the field effect transistor which limits power but also limits the voltage which can be applied to the load. The present invention protects field effect transistors without requiring a manual reset and without limiting the voltage applied to the load during normal operation.